The semiconductor transistors used to construct electronic memory devices are becoming progressively smaller, with the minimum channel width and channel lengths of the devices decreasing in value. This progression allows memory devices to become smaller, but the smaller channel lengths of the transistors have created more sub-threshold leakage current in the devices, particularly in CMOS devices. As is known in the art, sub-threshold current is the amount of current that leaks through the channel of the device, from source terminal to drain terminal along the channel length, when the transistor is placed in the “OFF” state (VGS<Vt, the threshold voltage). Because of certain three-dimensional effects in the device, notably the fringing of electric fields in the device during sub-threshold conditions, the leakage current increases as the channel length decreases even if the channel width decreases at the same rate. Furthermore, decreasing the channel width at a faster rate than the channel length does not rectify the problem. These problems are particularly evident in CMOS processes.
A typical semiconductor memory comprises tens to hundreds of bit lines, with each bit line receiving the outputs of tens to hundreds of memory cells. During each memory reading operation, one memory cell in the bit line is activated to couple its data state to the bit line for reading. All of the other memory cells in the bit line are deactivated. The selective coupling of the data is achieved by a transistor in each memory cell that is turned “ON” to couple the data to the bit line, or is turned “OFF” to not couple the data. With the above-noted leakage-current problem becoming more prevalent, the collective leakage current of all of the “OFF” transistors can swamp the data that the “ON” transistor is trying to couple to the bit line. As a practical matter, this places an upper limit on the number of memory cells that can be associated with each bit line. Thus, as the size of the transistors shrinks, to increase the size of the memory and/or to increase the speed performance of the memory, one has to find a way of somehow partitioning the bit line into several local bit lines that feed a global bit line. For register file memories, which are small memories having very high-speed performance, partitioning the bit line into several local bit lines which feed a global bit line would have the negative effects of decreasing speed performance and increasing size.
Thus, there is a need to overcome this apparent fundamental limitation in order to continue receiving the benefits of increased speed and reduced size that come from reducing the size of the transistors in the memories.